1. Field of the Invention
The present invention relates to package structures and fabrication methods thereof, and more particularly, to a package structure having conductive bumps and a fabrication method thereof.
2. Description of Related Art
As electronic products are developed toward the trend of multi-function, high electrical performance and high operational speed, there have been developed various types of semiconductor package modules. For example, a multi-chip module (MCM) integrates a plurality of chips in a semiconductor device so as to meet the requirement of electronic products.
FIGS. 1A and 1B are schematic cross-sectional views of semiconductor devices having a plurality of chips integrated therein. Referring to FIG. 1A, a plurality of semiconductor chips 11 are vertically stacked on a substrate 10. Alternatively, referring to FIG. 1B, a plurality of semiconductor chips 11 are horizontally disposed a substrate 10. However, electrical and reliability tests on the semiconductor chips 11 of FIGS. 1A and 1B can only be performed after a packaging process is completed. If any one of the semiconductor chips 11 fails the test, the overall semiconductor device must be discarded.
Accordingly, another type of semiconductor device is provided by U.S. Pat. No. 6,303,997. Referring to FIG. 1C, both a semiconductor chip 11 and a semiconductor package 12 are disposed on an upper surface of a substrate 10 and electrically connected to the substrate 10. To form the semiconductor device, the semiconductor chip 11 is first electrically connected to the substrate 10 through bonding wires 111 and a test is performed to the semiconductor chip 11. If it is determined that the semiconductor chip 11 functions normal, the BGA-type semiconductor package 12 that is already packaged and tested is then electrically connected to the substrate 10 through a plurality of solder balls 121. Thereafter, a test is performed to the overall structure, thus overcoming the above-described drawback of waste of known good dies.
However, to electrically connect the semiconductor chip 11 and the semiconductor package 12 to the substrate 10, a plurality of wire bonding pads and solder ball pads need to be formed on the substrate 10. As such, not only wiring on the substrate is limited, but also high density interconnect technologies, for example, built-up substrate technologies are required, thus incurring a high fabrication cost.
Accordingly, a further type of semiconductor device is disclosed by U.S. Pat. No. 5,783,870. Referring to FIG. 1D, a first semiconductor package 12a is electrically connected to a substrate 10 through a plurality of solder balls 121a. Further, a second semiconductor package 12b is stacked on a first semiconductor package 12a through a plurality of solder balls 121b, and similarly, a third semiconductor package 12c is stacked on the second semiconductor package 12b, thus forming a modular semiconductor device. As such, both the second semiconductor package 12b and the third semiconductor package 12c are electrically connected to the substrate 10. In addition, the semiconductor packages 12a, 12b, 12c are respectively tested before being disposed in a stack manner, thus overcoming the above-described drawback of waste of known good dies.
However, since a lower semiconductor package has a chip mounting area, the solder balls of an upper semiconductor package for electrically connecting the upper and lower semiconductor packages must be bonded to a region outside the chip mounting area, thereby limiting the electrically connecting area and wiring on the substrate as well as the I/O count and arrangement of the upper semiconductor package. Consequently, the design flexibility of the overall device is reduced.
Therefore, how to overcome the above-described drawbacks has become critical.